1. Field of the Invention
The invention relates to a method of forming a memory device, and more particularly, to a method of forming a flash memory device.
2. Description of the Related Art
Flash memory, which is a kind of electrically erasable and programmable read only memory (EEPROM), is currently one the most widely used memory devices applied in personal computers and electronic equipment. A memory cell in a flash memory comprises a transistor with a floating gate to achieve the operations of writing, erasing, and storing data while electrically shut down.
FIG. 1A is a schematic, cross-sectional view showing a conventional flash memory device. As shown in the figure, a memory region 102 and a peripheral circuit region 104 within a substrate 100 are isolated from each other by an isolating structure 101. A stacked gate 106 of a flash memory is formed on the memory region 102. A capacitor 108 of a transistor is formed on the peripheral circuit region 104. The stacked gate 106 comprises a tunneling oxide layer 110, a floating gate 112, a dielectric layer 114 and a control gate 116. The capacitor 108 comprises a gate oxide layer 118 and a conductive gate layer 120. A source/drain region 138 is formed in the memory region 102 to complete the flash memory. Another source/drain region 140 is formed in the peripheral circuit region 104 to complete the transistor.
To enhance the reliability of the flash memory, an oxidation step is usually used to partially oxidize the edge of the floating gate 112 above the tunneling oxide layer 110 to form an oxide layer 134 as shown in FIG. 1B. Forming the oxide layer 134 increases the total thickness of the tunneling oxide layer 110. However, the capacitor 108 in the peripheral circuit region 104 is exposed in an oxygen environment while performing the oxidation step. The conductive gate layer 120 is oxidized to form an oxide layer 135 above the edge of the gate oxide layer 118. The oxidation increases the total thickness of the gate oxide layer 118 to decrease a saturated current of the transistor and further to decrease an operation velocity of the flash memory device.